Synchronous digital systems, including board level systems and chip level systems, rely on one or more clock signals to synchronize elements across the system. Typically, one or more clock signals are distributed across the system on one or more clock lines. However, due to various problems such as clock buffer delays, high capacitance of heavily loaded clock lines, and propagation delays, the rising edges of a clock signal in different parts of the system may not be synchronized. The time difference between a rising (or falling) edge in one part of the system with the corresponding rising (or falling) edge in another part of the system is referred to as “clock skew”.
Clock skew can cause digital systems to malfunction. For example, it is common for circuits in digital systems to have a first flip-flop output driving a second flip-flop input. With a synchronized clock on the clock input of both flip-flops, the data in the first flip-flop is successfully clocked into the second flip-flop. However, if the active edge on the second flip flop is delayed by clock skew, the second flip-flop might not capture the data from the first flip-flop before the first flip-flop changes state.
Delay lock loops are used in digital systems to minimize clock skew. Delay lock loops typically use delay elements to synchronize the active edges of a reference clock signal in one part of the system with a feedback clock signal from a second part of the system. FIG. 1 shows a block diagram of a conventional delay lock loop 100 coupled to logic circuits 190. Delay lock loop 100, which comprises a delay line 110 and a phase detector 120, receives a reference clock signal REF_CLK and drives an output clock signal O_CLK.
Delay line 110 delays reference clock signal REF_CLK by a variable propagation delay D before providing output clock signal O_CLK. Thus, each clock edge of output clock signal O_CLK lags a corresponding clock edge of reference clock signal REF_CLK by propagation delay D (see FIG. 2A). Phase detector 120 controls delay line 110, as described below. Delay line 110 is capable of producing a minimum propagation delay D_MIN and a maximum propagation delay D_MAX.
Before output clock signal O_CLK reaches logic circuits 190, output clock signal O_CLK is skewed by clock skew 180. Clock skew 180 can be caused by delays in various clock buffers (not shown) or propagation delays on the clock signal line carrying output clock signal O_CLK (e.g., due to heavy loading on the clock signal line). To distinguish output clock signal O_CLK from the skewed version of output clock signal O_CLK, the skewed version is referred to as skewed clock signal S_CLK. Skewed clock signal S_CLK drives the clock input terminals (not shown) of the clocked circuits within logic circuits 190. Skewed clock signal S_CLK is also routed back to delay lock loop 100 on a feedback path 170. Typically, feedback path 170 is dedicated specifically to routing skewed clock signal S_CLK to delay lock loop 110. Therefore, any propagation delay on feedback path 170 is minimal and causes only negligible skewing.
FIG. 2A provides a timing diagram of reference clock signal REF_CLK, output clock signal O_CLK, and skewed clock signal S_CLK. All three clock signals have the same frequency F (not shown) and period P, and all are active-high (i.e., the rising edge is the active edge). Since output clock signal O_CLK is delayed by propagation delay D, a clock edge 220 of output clock signal O_CLK lags corresponding clock edge 210 of reference clock signal REF_CLK by propagation delay D. Similarly, a clock edge 230 of skewed clock signal S_CLK lags corresponding clock edge 220 of output clock signal O_CLK by a propagation delay SKEW, which is the propagation delay caused by clock skew 180 (FIG. 1). Therefore, clock edge 230 of skewed clock signal S_CLK lags clock edge 210 of reference clock signal REF_CLK by a propagation delay DSKEW, which is equal to propagation delay D plus propagation delay SKEW.
Delay lock loop 100 controls propagation delay D by controlling delay line 110. However, delay line 110 cannot create negative delay; therefore, clock edge 230 cannot be synchronized to clock edge 210. Fortunately, clock signals are periodic signals. Therefore, delay lock loop 100 can synchronize reference clock signal REF_CLK and skewed clock signal S_CLK by further delaying output clock signal O_CLK such that clock edge 240 of skewed clock signal S_CLK is synchronized with clock edge 210 of reference clock signal REF_CLK. As shown in FIG. 2B, propagation delay D is adjusted so that propagation delay DSKEW is equal to period P. Specifically, delay line 110 is tuned so that propagation delay D is increased until propagation delay D equals period P minus propagation delay SKEW. Although propagation delay DSKEW could be increased to any multiple of period P to achieve synchronization, most delay lock loops do not include a delay line capable of creating such a large propagation delay.
Phase detector 120 (FIG. 1) controls delay line 110 to regulate propagation delay D. The actual control mechanism for delay lock loop 100 can differ. For example, in one version of delay lock loop 100, delay line 110 starts with a propagation delay D equal to minimum propagation delay D_MIN, after power-on or reset. Phase detector 110 then increases propagation delay D until reference clock signal REF_CLK is synchronized with skewed clock signal S_CLK. In another system, delay lock loop 100 starts with a propagation delay D equal to the average of minimum propagation delay D_MIN and maximum propagation delay D_MAX, after power-on or reset. Phase detector 120 then determines whether to increase or decrease (or neither) propagation delay D to synchronize reference clock signal REF_CLK with skewed clock signal S_CLK. For example, phase detector 120 would increase propagation delay D for the clock signals depicted in FIG. 2A. However, phase detector 120 would decrease propagation delay D for the clock signals depicted in FIG. 2C.
In FIG. 2C, skewed clock signal S_CLK is said to “lag” reference clock signal REF_CLK, because the time between a rising edge of reference clock signal REF_CLK and the next rising edge of skewed clock signal S_CLK is less than the time between a rising edge of skewed clock signal S_CLK and the next rising edge of reference clock signal REF_CLK. However, in FIG. 2A, reference clock signal REF_CLK is said to “lag” skewed clock signal S_CLK, because the time between a rising edge of skewed clock signal S_CLK and the next rising edge of reference clock signal REF_CLK is less than the time between a rising edge of reference clock signal REF_CLK and the next rising clock edge of skewed clock signal S_CLK. Alternatively, in FIG. 2A skewed clock signal S_CLK could be said to “lead” reference clock signal REF_CLK.
After synchronizing reference clock signal REF_CLK and skewed clock signal S_CLK, delay lock loop 100 monitors reference clock signal REF_CLK and skewed clock signal S_CLK and adjusts propagation delay D to maintain synchronization. For example, if propagation delay SKEW increases, perhaps caused by an increase in temperature, delay lock loop 100 must decrease propagation delay D to compensate. Conversely, if propagation delay SKEW decreases, perhaps caused by a decrease in temperature, delay lock loop 100 must increase propagation delay D to compensate. The time in which delay lock loop 100 is attempting to first synchronize reference clock signal REF_CLK and skewed clock signal S_CLK, is referred to as lock acquisition. The time in which delay lock loop 100 is attempting to maintain synchronization is referred to as lock maintenance. The value of propagation delay D at the end of lock acquisition, i.e. when synchronization is initially established, is referred to as initial propagation delay ID.
However, as explained above, delay line 110 can only provide a propagation delay between a minimum propagation delay D_MIN and a maximum propagation delay D_MAX. During lock maintenance, delay lock loop 100 may lose synchronization if a propagation delay D smaller than minimum propagation delay D_MIN is required to maintain synchronization. Similarly, synchronization may be lost if a propagation delay D greater than maximum propagation delay D_MAX is required to maintain synchronization.
For example, if lock acquisition occurs while the system using delay lock loop 100 is at a very high temperature, delay lock loop 100 is likely to achieve synchronization with a very small initial propagation delay ID, since propagation delay SKEW is likely to be large with respect to period P. As the system's temperature increases further, propagation delay SKEW is likely to increase to a point where propagation delay SKEW plus minimum propagation delay D_MIN is greater than period P. In this situation, delay lock loop 100 must undergo lock acquisition again, which may introduce glitches and noise into output clock signal O_CLK, in turn causing glitches and noise in skewed clock signal S_CLK. For critical systems, such glitches are intolerable. Further, for systems designed for operation at multiple clock frequencies, low frequency operation is likely to compound the problems since clock period P is very long. Long clock periods may cause propagation delay D to vary over a wider time interval. Thus, there is a need for a delay lock loop which can maintain synchronization over a wide range of clock frequencies and environmental extremes.
In addition, conventional delay lock loop circuits provide for precise synchronization of the reference clock signal REF_CLK and the skew clock signal S_CLK. It would be desirable to have a delay lock loop circuit which is capable of providing a skew clock signal S_CLK which is precisely shifted by a relatively small amount with respect to the reference clock signal REF_CLK. It would further be desirable if such delay lock loop circuit were capable of providing both a leading and lagging relationship. Such a delay lock loop circuit would enable the precise control of clock phase in logic circuits. Such control allows, for example, more accurate timing budget allocation, which in turn, allows synchronous digital systems to run at faster speeds.
Delay lock loop circuit 100 provides an S_CLK signal having a single frequency in response to the REF_CLK signal. For example, the S_CLK signal may have a frequency of 100 MHz. The Federal Communications Commission (FCC) has provided limits on the electromagnetic energy that a chip may emit within a specified frequency bandwidth, which depends on the characteristics of the system being tested. One such measurement method employs a 1 MHz bandwidth window. Because all of the energy emitted by the S_CLK signal exists at a single frequency, all of the energy will also exist within such a window. Therefore, for systems that violate FCC limits, special techniques must be employed to reach compliance. Conventional compliance techniques include the use of stand-alone (i.e., off-chip) spread spectrum clock oscillators and metal shielding around the radiating components.
It would therefore be desirable to have a clock system that overcomes the electromagnetic emission limitations of delay lock loop 100.